The present invention relates to electronic circuits and, more particularly, to a charge pump circuit with self-generated boosted phases.
As is well known in semiconductor integrated non-volatile memory devices, it is often necessary to perform programming operations thus modifying the information content of the memory device. These programming operations may be a writing phase or an erasing phase. Generally, the first writing operation determines a logic xe2x80x9c0xe2x80x9d in the memory cells of the memory device, while the second erasing operation determines a logic xe2x80x9c1xe2x80x9d.
During the writing and erasing operations a voltage higher than the supply may be required. In many cases, negative voltage values are required and produced by charge pumps. For example, for the erasing phase of a single supply voltage flash memory device, all the driving terminals of the transistors forming the memory arrays, that is, all the terminals of the gate arrays, are driven by a voltage value of about xe2x88x929 V. A ramp potential is applied on the bulk or substrate terminal of these transistors and at the end of the erasing phase, when the last erasing pulse is generated, a voltage value of 8.75 V will be present.
The technical processes implemented to manufacture flash memory devices of the last generation are triple well processes allowing complete isolation of the semiconductor regions to which different voltage values are applied. The triple well technology allows realizing negative charge pumps by using N-channel MOS transistors.
The electrical schematic of an N-channel MOS transistor obtained by a triple well structure is shown in FIG. 1 as being part of a negative charge pump. As may be noted in FIG. 6, wherein the same transistor is shown in its real implementation, a suitable biasing of the buried N-doped region at the highest available voltage value, for instance the supply voltage value Vdd, allows a perfect isolation between the well region and the substrate. Such an isolation allows biasing the well region to a negative voltage value, thus, avoiding a direct bias between the well region and the substrate, and as a consequence, between the source and drain regions of the pass transistor.
The ideal condition for the well region is obtained by biasing it to the lowest possible voltage value available in the circuit. This causes a high body effect on the transistors performing the charge transfer. This could cause a low charge transfer efficiency between the pump stages at low supply voltage values.
A schematic view of a negative charge pump for semiconductor integrated memory devices having a single power supply and manufactured by a triple well process is shown in FIG. 1. There is also visible an enlarged scale particularly concerning a charge pass transistor. As shown in this FIG. 1, in the first stages of the charge pump the bulk terminals are biased with a voltage value that is available only two stages downstream. The last two stages have the bulk terminals simply connected to the output terminal. This charge pump architecture is a good compromise between the need to avoid a direct biasing on the parasitic diodes between the junctions, and the other need to limit the body effect that is always there.
As an example, with this architecture the voltages available to the terminals of the second stage pass transistor, in the conduction state, are shown in FIG. 2. The transistor shown in FIG. 2 sees a bulk voltage corresponding to the voltage value reached by the voltage two stages downstream, while the gate terminal sees a voltage corresponding to the voltage on the node 1 plus a voltage swing equal to the supply voltage and due to the inverters that work as phase drivers for the A, B, C and D phases. In this example, the charge transfer from the load capacitance toward ground is penalized by an undesired start-up of those transistors since they receive just the single supply voltage Vdd. In this manner the charge transfer from one stage to the other subsequent stage could be difficult when increasing the working frequency which is fixed by the required performance in terms of drive capability and setting time (Trise).
An imperfect charge transfer is immediately transformed into lower pump efficiency, or, in other words, poorer performance parameters as previously mentioned. Poorer performance is mainly noted in low voltage devices, for instance, those working with a supply voltage Vdd=1.8/2.5V.
An object of the present invention is provide a negative charge pump architecture having structural and functional features allowing a better charge transfer between the pump stages through a better voltage overdrive on the gates of the pass transistors.
A first embodiment of the invention provides a higher voltage swing on the node 1, shown in FIG. 2, for instance, by doubling the voltage overdrive on such a node passing from a common voltage swing corresponding to the supply voltage value to a double voltage swing corresponding to a double supply voltage value, as shown in FIGS. 3A and 3B.
To achieve this object, a negative voltage value Vdd is picked up by the same charge pump changing its architecture. Thus, the invention relates to a negative charge pump architecture comprising: a plurality of circuit stages cascade connected one to the other between an input stage, coupled to an input reference potential, and an output stage including an output terminal producing a pumped potential. The architecture further includes a corresponding plurality of a pass transistors, one for each stage, each driven by a corresponding phase signal through a decoupling capacitor, and a corresponding plurality of charge capacitances, one for each stage. In addition, the negative charge pump architecture may include a further output stage connected downstream of the input stage and including a further output terminal producing a further raised or pumped potential.